Nowadays, the semiconductor manufacturing industry has been developing under the guidance of Moore's law, the performance and the integrated density of integrated circuits being continually enhanced while the power consumption of the integrated circuits being reduced as much as possible. Accordingly, the fabrication of an ultra short channel device with high performance and low power consumption would become the focus in the future semiconductor manufacturing industry. After a 22-nanometer technology node comes, a leakage current of conventional planar field effect transistor has been continuously increasing and the short channel effect and the drain induced barrier lowering (DIBL) effect are becoming increasingly serious, which can not appropriately adapt to the development of the semiconductor manufacturing. In order to overcome a series of the above-mentioned problems, a mass of new-structured semiconductor device, such as Double Gate FET, FinFET, Tri-Gate FET, Gate-all-around (GAA) Nanowire (NW) FET and so forth are emerging and gradually drawing wide attention. By means of a multi-gate structure, the gate control ability to a channel can be desiredly enhanced so that electric field lines have difficulties in directly passing through the channel from a drain to a source. Thus, the drain induced barrier lowering effect can be dramatically ameliorated, the leakage current can be reduced, and the short channel effect can be substantially inhibited. Owing to the face that the multi-gate structure has resulted in an good gate control ability, unlike in the conventional planar field effect transistor, it is not necessary for the channel region to be heavily doped to suppress the short channel effect. Since a lightly-doped channel area has advantages in reducing the drop of the mobility due to the scattering, the mobility of the multi-gate structured device can be greatly improved. Therefore, the FinFET, as a new-structured device, would be capable of becoming a promising alternative to the conventional planar field effect transistor.
A concept of “folded-channel MOSFETs” was proposed in the IEDM conference in 1998 by Hasimoto et al. And in 1999, a FinFET with a channel length below 50 nm was disclosed in the IEDM conference. That was the first time to successfully integrate the FinFET on a substrate by using a conventional silicon process.
A structure of the FinFET and a process for fabricating the same were disclosed in U.S. Pat. No. 6,413,802 by Hu et al. The FinFET can be formed on a SOI substrate most easily, the process being relatively simple, where the FinFET can be formed just by photoetching a top silicon layer on the SOI substrate to form a pattern of a Fin bar and then performing a series of processings such as a gate processing, a source/drain processing and a back-ended interconnection of a dielectric layer and a metal. However, it has disadvantages as follows: (1) a process cost is too high due to the quite expensive SOI substrate; (2) it is necessary to perform a source/drain lifting technology, or else a spreading resistance of the source/drain would be too high, resulting in an excessively small on-current and thus poorer device performance; (3) due to the absence of a body leading-out, a threshold voltage cannot be adjusted by means of a substrate bias effect. Meanwhile, in the case that the FinFET is formed on a bulk silicon substrate, the issue is avoided that the source/drain spreading resistance is too high, and moreover, a voltage can also be applied to a body terminal to obtain the substrate bias effect so that the threshold voltage may be adjusted more easily to a more appropriate value. Nevertheless, it also has its own disadvantages as follows: (1) the process is relatively complicated and the requirement for control of the process is even higher, since it is necessary to add an oxidation isolation layer to the FinFET so as to suppress a turning-on of a bottom planar transistor and reduce the leakage current; (2) although the oxidation isolation layer is added, due to the presence of a further current path from the source to the drain in addition to the Fin bar, the gate control ability is not as excellent as that of the device fabricated on the SOI substrate, resulting in that the power consumption due to the leakage current in the ultra short channel device remains larger.